1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a redundant means in a semiconductor memory device in which ROMs and RAMs are both present in one chip. The present invention also relates to a redundant means in a semiconductor memory device in which ROMs and RAMs are both present on one line (a row or column line).
2. Description of the Related Art
FIG. 14 shows a part of a circuit in a conventional semiconductor memory device in which ROM cells 35 and RAM cells 34 are both present in one chip. FIG. 14 schematically shows a memory cell array 1, a row decoder 2, a column decoder 3, a data line readout circuit 5, word lines 30, bit line pairs 47, etc. of the semiconductor memory device.
In the memory cell array 1, the memory cells are arranged on row lines and column lines. The "row line" herein corresponds to the word line 30, and the "column line" herein corresponds to the bit line pair 47. In the semiconductor memory device shown in FIG. 14, the ROM cells 35 and the RAM cells 34 are both present on each column line.
A number of the word lines 30 in a memory block shown in FIG. 14 is 256. The row decoder 2 decodes row addresses (RA0-RA7), thereby selecting one word line from the 256 word lines 30. The word line 30 selected when all the row addresses (RA0-RA7) are 0 is taken as a 0th word line. The word line 30 selected when all the row addresses (RA0-RA7) are 1 is taken as a 255th word line. One address in the memory cell array 1 is designated by a first address signal (a column address signal) for selecting one line in the memory cell array 1 and a second address signal (a row address signal) for selecting one address on the selected line.
FIGS. 11a and 11b show an example of the column decoder 3 and the row decoder 2, respectively. The row decoder 2 decodes a row address signal to activate one word line among the plurality of the word lines 30. The column decoder 3 decodes a column address signal to activate one of a plurality of column selecting signal lines 46. Memory cells belonging to the word line 30 which has been selected, i.e., activated, are electrically connected to the bit line pairs 47, thereby causing a potential difference in each of the bit line pairs 47 in response to the data stored in the selected memory cells.
The potential difference is amplified by a sense amplifier 37. A potential difference in the bit line pair 47 selected by the column selecting signal line 46 is output to a data line pair 6 (hereinafter referred to as the "data line") via a transfer gate. The potential difference output to the data line 6 is amplified by the data readout circuit 5 and transferred to an output circuit 4.
This semiconductor memory device comprises both ROM cells and RAM cells in one memory cell array. As a result, the ROM cells and the RAM cells are both present on one line in the memory block shown in FIG. 14.
FIG. 17 shows the construction of the semiconductor memory device comprising a plurality of the memory blocks as shown in FIG. 14. FIG. 18 shows the construction of a semiconductor memory device comprising both ROM cells and RAM cells in one chip, in which each memory block includes either ROM cells or RAM cells.
Next, the structures of the RAM cell 34 and the ROM cell 35 will be described referring to FIGS. 20a through 20d. FIG. 20a shows a first example of the RAM cell 34. This RAM cell 34 is a known DRAM cell. Its operations such as a readout operation are well known. FIG. 20b shows a first example of the ROM cell 35. This ROM cell 35 has a structure in which a potential of a storage node a1 in the DRAM cell as shown in FIG. 20a is fixed to Vcc or GND. The operations such as a readout operation of such a ROM cell 35 can be performed by the same method as in the DRAM cell as shown in FIG. 20a. Data is written in this ROM cell 35 in the earlier step (a wafer process) as follows: Data, 1 or 0, is stored in each ROM cell 35 by varying a connection shown with an arrow in FIG. 20b by varying the pattern on a photomask.
FIG. 20c shows a second example of the RAM cell 34. This RAM cell 34 is a known SRAM cell. Its operations such as a readout operation are also well known. FIG. 20d shows a second example of the ROM cell 35. This ROM cell 35 has a structure in which potentials of nodes c1 and c2 in a flip flop of an SRAM cell as shown in FIG. 20c are fixed to Vcc and GND or GND and Vcc, respectively. Therefore, the operations such as a readout operation of such a ROM cell 35 can be performed by the same method as in the SRAM cell as shown in FIG. 20c.
FIG. 15 shows a part of a conventional RAM cell block having a redundant element. Like reference numerals are used to refer to like elements throughout.
In order to recover a defective line redundantly, a line of memory cells including a defective bit (a defective line) is deactivated, and a redundant RAM bit line pair 347 is selected instead of the defective line. Memory cells 34 on the redundant RAM bit line pair 347 are generally disposed adjacent to the ordinary RAM cells 34 in the memory cell array 1. This is because the structure of the RAM cell 34 on the redundant RAM bit line pair 347 can be identical to that of the ordinary RAM cells 34. The RAM cells 34 on the redundant RAM bit line pair 347 can be operated in the same manner as the ordinary RAM cells 34.
FIG. 21 shows an example of a circuit for a redundant RAM column decoder 303. By using this column decoder 303, it is possible to program the column address of a defective line to be replaced in the later step after the wafer test. When the redundant column address which has been programmed corresponds to an externally input column address, a redundant RAM column selecting signal is output. The column address is programmed by melting fuses selected among a plurality of address program fuses depending upon each address. When the column decoder 303 shown in FIG. 21 is used as a row decoder, the wording "column address" in the above description should read the "row address".
A redundant replacement in the semiconductor memory device having the redundant RAM bit line pair 347 will now be described. The column address of a bit line pair 47 including a defective bit is programmed in the redundant RAM column decoder 303. As shown in FIG. 21, a pair of fuses corresponds to one bit in the column address. By melting one of the fuses by using a laser trimming, the defective column address can be memorized. A redundant RAM column activating fuse is also melted at the same time as the melting of the above fuse. When the redundant RAM column activating fuse is melted, a node (a control terminal) 13a is defined to be at a high level in switching on a power supply. When this fuse is not melted, the node 13a is always at a low level. When the node 13a is at the low level, the output terminals of an inverter 13b with a control terminal and a buffer 13c with a control terminal are in a high impedance state. When the node 13a is at the high level, signals can be output on the output terminals of the inverter 13b and the buffer 13c. Therefore, when the redundant RAM activating fuse is melted, a redundant RAM column selecting signal is output if the programmed redundant column address corresponds to an externally input column address. When the redundant RAM activating fuse is not melted, a redundant RAM column selecting signal is not output since the input of an AND circuit is always at the low level.
Moreover, the defective address is deactivated in the column decoder as shown in FIG. 11a so as not to select the column address on the defective bit line as follows: Fuses corresponding to a column selecting signal for the defective column in the column decoder as shown in FIG. 11a are melted by using a laser trimming. As a result, a column selecting signal 46 for the defective column is not output.
FIG. 16 shows a part of a conventional ROM cell block having a redundant element.
In order to recover a defective line redundantly, a bit line 147 including a defective bit (a defective line) is deactivated, and when the defective line is selected, a redundant ROM bit line 247 is selected instead. Redundant ROM cells 36 on the redundant ROM bit line 247 are generally disposed outside of the memory cell array 1 independently from the ordinary ROM cells 35. This is because the redundant ROM cell 36 is larger than the ordinary ROM cell 35 in the memory cell array 1. A redundant ROM row decoder 202b for the redundant ROM bit line 247 is provided independently from the ordinary row decoder 2.
This circuit for the ROM cells is different from that of the RAM cells shown in FIG. 15 in the following: The bit line pair 47 is replaced with the bit line 147. The sense amplifier 37 is provided not to each bit line 147 but to each memory cell array 1. A bit line selected by the column decoder 3 is connected to the single sense amplifier 37.
FIG. 21 shows an example of a circuit for the redundant ROM column decoder 203. By using this redundant ROM column decoder 203, a column address on the defective line to be replaced can be programmed in the later step after the wafer test. When the programmed redundant column address corresponds to an externally input column address, a redundant ROM column selecting signal is output. The column address is programmed by melting fuses selected among a plurality of the address program fuses depending upon each address.
The redundant ROM bit line 247 in FIG. 16 will now be described in detail.
An example of the redundant ROM cell 36 on the redundant ROM bit line 247 is shown in FIG. 20e. The ROM data can be written in the redundant ROM cells 36 depending upon whether or not the fuse shown in FIG. 20e is melted by using a laser trimming in the later step after a wafer process and the wafer test. The structure of the memory cell shown in FIG. 20e can be readily understood when compared with that of a known mask ROM cell shown in FIG. 20f. Whether or not the fuse in the memory cell of FIG. 20e is melted indicates whether or not the threshold value of the mask ROM cell of FIG. 20f is high. Therefore, operations such as the readout of the redundant memory cell can be performed in the same manner as a known mask ROM cell.
A redundant replacement of a semiconductor memory device having the redundant ROM bit line will now be described.
A column address on a bit line including a defective bit is programmed in the redundant ROM column decoder as shown in FIG. 21. A pair of fuses corresponds to one bit of the column address. The address of the defective line can be memorized by melting one of the pair of fuses by using a laser trimming. A redundant ROM column activating fuse is melted at the same time as the melting of the above fuse. When the redundant ROM column activating fuse is melted, the node 13a is defined to be at the high level in switching on a power supply. When this fuse is not melted, the node 13a is always at the low level. When the node 13a is at the low level, the output terminals of the inverter 13b with a control terminal and the buffer 13c with a control terminal are in a high impedance state. When the node 13a is at the high level, signals can be output on the output terminals of the inverter 13b and the buffer 13c. Therefore, when the redundant ROM activating fuse is melted, a redundant ROM column selecting signal 48 is output if the programed redundant column address corresponds to an externally input column address. When the redundant ROM activating fuse is not melted, the redundant ROM column selecting signal 48 is not output since the input of an AND circuit is always at the low level.
Moreover, the defective address is deactivated in the column decoder as shown in FIG. 11b so as not to select the column address on the defective bit line as follows: Fuses corresponding to a column selecting signal for the defective column in the column decoder as shown in FIG. 14 are melted by using a laser trimming. As a result, a column selecting signal 46 for the defective column is not output. Further, data on the ROMs on the defective line are programmed in the ROM cells 36 in the row addresses on the redundant ROM bit line 247. Namely, fuses corresponding to a desired row address are melted.
FIG. 12 shows a redundant ROM row decoder 202b. The redundant ROM row decoder 202b receives a row address signal and the redundant ROM column selecting signal 48, and activates the designated one redundant ROM row selecting signal line 31 when the redundant ROM column selecting signal 48 is activated. In this manner, a redundant ROM cell 36 selected by the redundant ROM row selecting signal line 31 is connected to the redundant ROM bit line 247. Data on the redundant ROM bit line 247 is read out by a redundant ROM bit line readout circuit 205 and transferred to the output circuit 4. The sense amplifier 37 works when the redundant ROM column selecting signal is not activated, and the redundant ROM bit line readout circuit 205 works when the redundant ROM selecting signal is activated. Thus, a defective line of ROMs is recovered redundantly.
In order to produce a semiconductor memory device in which ROM cells and RAM cells are both present, a redundant technique for replacing a memory cell in which a defect has been caused in the production process with a spare memory cell is indispensable to increase the yield. However, a conventional RAM redundant is effective only in the redundant recovery of a memory cell array including RAM cells alone, and a conventional ROM redundant is effective only in the redundant recovery of a memory cell array including ROM cells alone.
A semiconductor memory device including both RAM and ROM cells requires redundant elements for both ROM and RAM cells, respectively. Specifically, in a semiconductor memory device including both ROM and RAM cells in one chip as shown in FIG. 18, it is necessary to provide a redundant element for ROM cells or RAM cells to each memory cell array as shown in FIG. 19.
Alternatively, in a semiconductor memory device including both ROM and RAM cells in one memory cell array as shown in FIG. 17, when a defective line (a row or column line) including both ROM and RAM cells is replaced with, for example, a redundant RAM line, all the memory cells on the replaced line become RAM cells as shown in FIG. 22. On the contrary, when the defective line is replaced with a redundant ROM line, all the memory cells on the replaced line become ROM cells as shown in FIG. 23.
When the defective line is replaced with a redundant ROM line and a redundant RAM line as shown in FIG. 24, a butting between an address on the replaced redundant ROM line and that on the replaced redundant RAM line is caused. This butting will be described in detail referring to FIG. 24.
FIG. 24 is a schematic view of a semiconductor memory device in which ROM cells and RAM cells are both present on one line and in which data is written in a ROM cell in the earlier step. This semiconductor memory device requires both a redundant RAM line and a redundant ROM line in which data can be written in the later step, because both ROM cells and RAM cells on a defective line should be replaced to redundantly recover a defective line. When a redundant RAM line and a redundant ROM line are replaced with a defective line, addresses on both the redundant RAM line and the redundant ROM line are arranged on addresses on the same defective line. Therefore, when the defective line is designated by a first address signal, the redundant RAM line and the redundant ROM line are both selected, thereby causing a butting.
As described above, in a semiconductor memory device in which ROM cells and RAM cells are both present on one line, it has been impossible to redundantly recover a defective line. Therefore, such a semiconductor memory device has a poor yield, and it has been difficult to produce such a semiconductor memory device.